This invention relates to apparatus for providing circuits as logic gates to perform logical functions in combinational and sequential switching logic systems. Moreover, these logic gate circuits can be particularly advantageously provided as monolithic integrated circuits.
The advent of large scale integration has meant that monolithic integrated circuits are becoming available with more and more digital system functions provided therein to the point that substantial portions of many digital systems are provided on a single chip. This increase in functional density and so in circuit density in a monolithic integrated circuit has several advantages. Substantial economies are realized in reduced assembly costs, etc. Improved reliability results because fewer interconnections are needed to be made among the devices making up the system. There is an increase in the rapidity of operations since the signals which must be transmitted in the system need only be transmitted over small distances.
These advantages and others motivate the desire to increase the number of logic gates in a monolithic integrated circuit chip to further increase the logic function density, and so increase the portions of digital systems provided in such a device. Additionally, for the purpose of accomplishing more rapidly the logic functions to be performed to thereby improve the digital system capabilities, increasing the rapidity of operation of the logic gates used in the monolithic integrated circuit device is also very desirable. Yet, both increases in circuit density and in the rapidity of circuit searching operations tend to also increase the power dissipated in a monolithic integrated circuit device. Hence, the method chosen to reach these two goals must also provide for achieving a sufficiently low power dissipation if a viable monolithic integrated circuit device is to be realized.
Currently, the need for rapidly operating digital monolithic integrated circuit devices is most commonly met by transistor-transistor logic circuits (TTL), particularly Schottky-clamped TTL, and emitter-coupled logic (ECL). The logic gates provided in these logic families tend to use on the average more than one transistor per logic function accomplished. Use of one transistor per logical function would be quite desirable since the use of further transistors tends to require more space in a monolithic integrated circuit, tends to slow operation of the logic gate and tends to increase power consumption.
There have been attempts to develop new logic circuits to improve on the foregoing logic circuit families and to develop new logic families. Among these is a logic circuit shown in U.S. Pat. No. 3,769,524 to Mathews which teaches use of a NOR gate to perform logical functions. The circuitry shown in this patent teaches a somewhat simplified logic gate requiring relatively little power but still shows use of more than one transistor on the average in achieving the NOR logic function provided.
A substantial further improvement along these lines is shown in U.S. Pat. No. 3,970,866 to the present inventor and assigned to the present assignee. There is shown logic gate circuits having but one transistor per logic function and which can operate at a relatively low voltage to increase rapidity of operation and reduce power dissipation. Nevertheless, further improvements in density and reduced operating voltage are desirable.